? semiconductor components industries, llc, 2006 june, 2006 ? rev. 7 1 publication order number: mc14553b/d mc14553b 3?digit bcd counter the mc14553b 3?digit bcd counter consists of 3 negative edge triggered bcd counters that are cascaded synchronously. a quad latch at the output of each counter permits storage of any given count. the information is then time division multiplexed, providing one bcd number or digit at a time. digit select outputs provide display control. all outputs are ttl compatible. an on?chip oscillator provides the low?frequency scanning clock which drives the multiplexer output selector. this device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications. features ? ttl compatible outputs ? on?chip oscillator ? cascadable ? clock disable input ? pulse shaping permits very slow rise times on input clock ? output latches ? master reset ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ?0.5 to v dd + 0.5 v input current (dc or transient) per pin i in 10 ma output current (dc or transient) per pin i out +20 ma power dissipation, per package (note 1) p d 500 mw ambient temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c lead temperature (8?second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circui try to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. device package shipping ordering information mc14553bcp pdip?16 25 units / rail mc14553bdw soic?16 47 units / rail http://onsemi.com MC14553BCPG pdip?16 (pb?free) 25 units / rail marking diagrams a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package 1 so?16w dw suffix case 751g 16 1 mc14553b awlyyww figure 1. block diagram 12 10 11 13 9 7 6 5 14 2 1 15 v dd = pin 16 v ss = pin 8 43 clock le dis mr q0 q1 q2 q3 o.f. ds 1 ds 2 ds 3 cia cib pdip?16 p suffix case 648 16 1 mc14553bcp awlyywwg 1
mc14553b http://onsemi.com 2 truth table inputs outputs master reset clock disable le 0 0 0 no change 0 0 0 advance 0 x 1 x no change 0 1 0 advance 0 1 0 no change 0 0 x x no change 0 x x latched 0 x x 1 latched 1 x x 0 q0 = q1 = q2 = q3 = 0 x = don?t care ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 4.6 vdc) source ? (v oh = 9.5 vdc) pin 3 (v oh = 13.5 vdc) i oh 5.0 10 15 ? 0.25 ? 0.62 ? 1.8 ? ? ? ? 0.2 ? 0.5 ? 1.5 ? 0.36 ? 0.9 ? 3.5 ? ? ? ?0.14 ?0.35 ?1.1 ? ? ? madc (v oh = 4.6 vdc) source ? (v oh = 9.5 vdc) other (v oh = 13.5 vdc) outputs 5.0 10 15 ? 0.64 ? 1.6 ? 4.2 ? ? ? ? 0.51 ? 1.3 ? 3.4 ? 0.88 ? 2.25 ? 8.8 ? ? ? ? 0.36 ? 0.9 ? 2.4 ? ? ? madc (v ol = 0.4 vdc) sink ? (v ol = 0.5 vdc) pin 3 (v ol = 1.5 vdc) i ol 5.0 10 15 0.5 1.1 1.8 ? ? ? 0.4 0.9 1.5 0.88 2.25 8.8 ? ? ? 0.28 0.65 1.20 ? ? ? madc (v ol = 0.4 vdc) sink ? other (v ol = 0.5 vdc) outputs (v ol = 1.5 vdc) 5.0 10 15 3.0 6.0 18 ? ? ? 2.5 5.0 15 4.0 8.0 20 ? ? ? 1.6 3.5 10 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) mr = v dd i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.010 0.020 0.030 5.0 10 20 ? ? ? 150 300 600 adc total supply current (note 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.35 a/khz) f + i dd i t = (0.85 a/khz) f + i dd i t = (1.50 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.004.
mc14553b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (note 5) (c l = 50 pf, t a = 25 c) characteristic figure symbol v dd min typ (note 6) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns 2a t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns clock to bcd out 2a t plh , t phl 5.0 10 15 ? ? ? 900 500 200 1800 1000 400 ns clock to overflow 2a t phl 5.0 10 15 ? ? ? 600 400 200 1200 800 400 ns reset to bcd out 2b t phl 5.0 10 15 ? ? ? 900 500 300 1800 1000 600 ns clock to latch enable setup time master reset to latch enable setup time 2b t su 5.0 10 15 600 400 200 300 200 100 ? ? ? ns removal time latch enable to clock 2b t rem 5.0 10 15 ? 80 ? 10 0 ? 200 ? 70 ? 50 ? ? ? ns clock pulse width 2a t wh(cl) 5.0 10 15 550 200 150 275 100 75 ? ? ? ns reset pulse width 2b t wh(r) 5.0 10 15 1200 600 450 600 300 225 ? ? ? ns reset removal time ? t rem 5.0 10 15 ? 80 0 20 ? 180 ? 50 ? 30 ? ? ? ns input clock frequency 2a f cl 5.0 10 15 ? ? ? 1.5 5.0 7.0 0.9 2.5 3.5 mhz input clock rise time 2b t tlh 5.0 10 15 no limit ns disable, mr, latch enable rise and fall times ? t tlh , t thl 5.0 10 15 ? ? ? ? ? ? 15 5.0 4.0 s scan oscillator frequency (c1 measured in f) 1 f osc 5.0 10 15 ? ? ? 1.5/c1 4.2/c1 7.0/c1 ? ? ? hz 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14553b http://onsemi.com 4 figure 2. 3?digit counter timing diagram (reference figure 4) 1000 999 998 997 996 995 994 993 992 991 990 901 900 899 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 units clock units q0 units q1 units q2 units q3 tens clock tens q0 tens q3 hundreds clock hundreds q0 hundreds q3 disable overflow master reset scan oscillator digit select 1 digit select 2 digit select 3 up at 80 up at 980 up at 800 (disables clock when high) units tens hundreds pulse generator (a) 16 v dd q3 q2 q1 q0 o.f. ds 1 ds 2 ds 3 8v ss c le dis mr c l c l c l c l c l generator 1 (b) v dd q3 q2 q1 q0 o.f. ds 1 ds 2 ds 3 v ss c le mr dis c l c l c l c l c l generator 2 generator 3 20 ns 20 ns 90% 10% t plh t phl 50% 50% t thl t tlh 10% 90% 50% 1/f cl t wl(cl) 999 1000 t tlh 50% overflow bcd out clock 90% 10% t rem t phl , t plh 50% 50% 50% t wh(r) t su t phl master reset bcd out latch enable clock figure 3. switching time test circuits and waveforms t su t phl
mc14553b http://onsemi.com 5 operating characteristics the mc14553b three?digit counter, shown in figure 4, consists of three negative edge?triggered bcd counters which are cascaded in a synchronous fashion. a quad latch at the output of each of the three bcd counters permits storage of any given count. the three sets of bcd outputs (active high), after going through the latches, are time division multiplexed, providing one bcd number or digit at a time. digit select outputs (active low) are provided for display control. all outputs are ttl compatible. an on?chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. the frequency of the oscillator can be controlled externally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. multiple devices can be cascaded using the overflow output, which provides one pulse for every 1000 counts. the master reset input, when taken high, initializes the three bcd counters and the multiplexer scanning circuit. while master reset is high the digit scanner is set to digit one; but all three?digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. the disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. a pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. information can be recovered from the latches after the counters have been reset if latch enable remains high during the entire reset cycle. figure 4. expanded block diagram pulse shaper clock 12 11 disable (active high) c r q0 q1 q2 q3 10 units c r q0 q1 q2 q3 10 tens c r q0 q1 q2 q3 10 hundreds 10 latch enable quad latch quad latch quad latch r r scan oscillator scanner pulse generator c1 4 3 c1 a c1 b multiplexer 9 7 6 5 q0 q1 q2 q3 bcd outputs (active high) 13 14 2115 mr (active high) overflow ds 1ds 2ds 3 (lsd) digit select (msd) (active low)
mc14553b http://onsemi.com 6 figure 5. six?digit display v dd strobe reset clock input 10 13 56791512 14 3 4 12 11 clk dis q3 q2 q1 q0 ds3 ds2 ds1 c1 a c1 b o.f. 0.001 f 5 3 2 4 6 1 7 a b c d ph ld bi a b c d e f g 9 10 11 12 13 15 14 mc14543b lsd v dd displays are low current leds (i peak < 10 ma per segment) msd v dd 5 3 2 4 6 1 7 a b c d ph ld bi a b c d e f g 9 10 11 12 13 15 14 mc14543b 10 13 56791512 14 3 4 12 11 clk dis q3 q2 q1 q0 ds3 ds2 ds1 c1 a c1 b o.f. mc14553b mc14553b le mr le mr
mc14553b http://onsemi.com 7 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip?16 case 648?08 issue t
mc14553b http://onsemi.com 8 package dimensions so?16 wb case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 mc14553b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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